Design-Reuse

IP Verification : RTL prototyping: a hardware/software co-verification solution

Traditional ASIC and IP verification methods cannot adequately exercise the hardware and software components of today's designs. This is due to tool performance limitations, which impose a bottleneck ...
Design-Reuse

Blue Pearl Software Streamlines RTL Verification for Xilinx All Programmable FPGAs and SoCs

SANTA CLARA, California, Jul. 25, 2017 – Blue Pearl Software, Inc., the leading provider of design automation software for ASIC, FPGA and IP RTL verification, today announced Visual Verification Suite ...
EDN

Software increases RTL design productivity

The Cadence Joules RTL Design Studio allows front-end engineers to accelerate and improve register transfer level (RTL) design and implementation. By providing access to the physical information ...
EDN

Compiler abstracts RTL for software development

Santa Cruz, Calif. – EDA startup Carbon Design Systems Inc. will open a new approach to presilicon system validation with the launch of its SpeedCompiler and DesignPlayer tools in December. The tools ...
Semiconductor Engineering

Blurring The Lines On Prototyping

Prototyping is an integral part of every SoC today, with two main approaches being used: virtual or software-based, and physical, which includes FPGA-based boards as well as hardware emulation systems ...